Whatsapp
Posted : Friday, October 13, 2023 03:36 PM
Job Description
About our organization:
This position is within the Design Enablement (DE) organization of Technology Development.
The Runset Development team within this organization is looking for talented individuals to develop physical layout verification software (DRC, LVS, RC extraction) and support the latest Intel technologies and microprocessor designs.
As part of the Design Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of talented engineers solving challenging technical problems, enabling PDKs for Intel's most advanced process technologies, and drive PDKs towards industry standard methods and ease of use for the end customers.
About the job: The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors, and product design teams to develop and deliver high quality technology collaterals, models, and enablement of EDA tools.
Responsibilities include: Develop physical layout verification design rule checker (DRC), Layout vs Schematic (LVS), and RC extraction runsets using industry standard EDA tools (Synopsys ICV, Siemens/Mentor Calibre, and Cadence Pegasus)Work with the process development teams at Intel to define specifications for DRC, LVS, and RC extraction runsets.
Coordinate development of technology features, develop QA plans, and drive test-cases development working with relevant stakeholders.
Support PDK development and Intel design teams to debug and enhance runset quality and enhance runtime and usability of the runsets.
Engage with internal partners and external EDA vendors to coordinate tool feature requirements and specification.
Assess architecture and hardware limitations, plans technical projects in the design and development of CAD software.
Help library teams at Intel with technology path finding activities.
Important behavior traits we look for: Creative, independent, and out of the box thinker with strong problem-solving skills and analytical ability.
Drive innovation and initiatives to enhance existing automation, tools, and methodology.
Identify and analyze problems, plans, tasks, and solutions.
Cultivate and reinforce appropriate group values, norms, and behaviors.
Perform in a dynamic and challenging environment with drive and creativity.
This is an entry level position and will be compensated accordingly.
#DesignEnablement Qualifications You must possess the below minimum qualifications to be initially considered for this position.
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.
Minimum Qualifications: Candidate must possess a MS degree with 6+ months of experience or PhD degree with 1+ years of experience in Computer Science or Computer Engineering or Electrical Engineering or related field .
6+ months of experience in the following: -Unix or Linux operating system.
-With at least one of the following: C++, Python, Perl, TCL.
Preferred Qualifications: 6+ months of experience in the following: - Software repository management tools like Git.
- DRC/LVS/Extraction runsets and EDA tools (Synopsys ICV, Siemens/Mentor Calibre, and Cadence Pegasus, and simulation tools).
- VLSI design process, reliability verification, ESD concepts, standard cell library, and memory architectures.
- Semiconductor device physics, models, parasitic extraction, and technology scaling.
Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art - from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.
Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
Other Locations US, TX, Austin; US, AZ, Phoenix; US, CA, Santa Clara Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits We offer a total compensation package that ranks among the best in the industry.
It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.
Find more information about all of our Amazing Benefits here.
Annual Salary Range for jobs which could be performed in US, California: $102,540.
00-$153,580.
00 *Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs.
JobType Hybrid
The Runset Development team within this organization is looking for talented individuals to develop physical layout verification software (DRC, LVS, RC extraction) and support the latest Intel technologies and microprocessor designs.
As part of the Design Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of talented engineers solving challenging technical problems, enabling PDKs for Intel's most advanced process technologies, and drive PDKs towards industry standard methods and ease of use for the end customers.
About the job: The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors, and product design teams to develop and deliver high quality technology collaterals, models, and enablement of EDA tools.
Responsibilities include: Develop physical layout verification design rule checker (DRC), Layout vs Schematic (LVS), and RC extraction runsets using industry standard EDA tools (Synopsys ICV, Siemens/Mentor Calibre, and Cadence Pegasus)Work with the process development teams at Intel to define specifications for DRC, LVS, and RC extraction runsets.
Coordinate development of technology features, develop QA plans, and drive test-cases development working with relevant stakeholders.
Support PDK development and Intel design teams to debug and enhance runset quality and enhance runtime and usability of the runsets.
Engage with internal partners and external EDA vendors to coordinate tool feature requirements and specification.
Assess architecture and hardware limitations, plans technical projects in the design and development of CAD software.
Help library teams at Intel with technology path finding activities.
Important behavior traits we look for: Creative, independent, and out of the box thinker with strong problem-solving skills and analytical ability.
Drive innovation and initiatives to enhance existing automation, tools, and methodology.
Identify and analyze problems, plans, tasks, and solutions.
Cultivate and reinforce appropriate group values, norms, and behaviors.
Perform in a dynamic and challenging environment with drive and creativity.
This is an entry level position and will be compensated accordingly.
#DesignEnablement Qualifications You must possess the below minimum qualifications to be initially considered for this position.
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.
Minimum Qualifications: Candidate must possess a MS degree with 6+ months of experience or PhD degree with 1+ years of experience in Computer Science or Computer Engineering or Electrical Engineering or related field .
6+ months of experience in the following: -Unix or Linux operating system.
-With at least one of the following: C++, Python, Perl, TCL.
Preferred Qualifications: 6+ months of experience in the following: - Software repository management tools like Git.
- DRC/LVS/Extraction runsets and EDA tools (Synopsys ICV, Siemens/Mentor Calibre, and Cadence Pegasus, and simulation tools).
- VLSI design process, reliability verification, ESD concepts, standard cell library, and memory architectures.
- Semiconductor device physics, models, parasitic extraction, and technology scaling.
Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art - from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.
Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
Other Locations US, TX, Austin; US, AZ, Phoenix; US, CA, Santa Clara Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits We offer a total compensation package that ranks among the best in the industry.
It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.
Find more information about all of our Amazing Benefits here.
Annual Salary Range for jobs which could be performed in US, California: $102,540.
00-$153,580.
00 *Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs.
JobType Hybrid
• Phone : NA
• Location : Phoenix, AZ
• Post ID: 9003724498
