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Posted : Tuesday, July 16, 2024 12:01 AM
Job Description
The Server and IP Engineering Group (SIPG) organization is responsible for developing leadership IPs that are power-winning products for our customers and Intel.
SIPG develops a broad portfolio of IP, including FIP, analog IP, Die to Die communication.
The Customer Engineering Group (CEG) within SIPG will be a dynamic and versatile team of engineers who directly engage with both the IP design teams and external customers in all phases of development.
CEG engineers will embody customer obsession by quickly resolving customer issues and providing hands-on debugging on a wide range of technical issues spanning all design domains (logic design, timing, physical integration, emulation, documentation, and customer training).
Your job responsibilities may include but are not limited to the following: Work with cross-functional teams for IP Integration into SoC.
Engage with IP development team to ensure all IP collaterals are generated and provided.
Fully own assigned IPs and work with Internal and external customers and help them integrate Intel IPs to SoC and provide technical support.
Drive resolution of customer issues related to the IP collaterals generation, logic design verification, IP release, and integration in the SoC environment.
This may involve travel to customer sites.
Engage in the upfront identification and documentation of customer requirements, working with the IP design teams to disposition requests.
Prepare customer training materials and provide training on IP architecture, specifications, and fuse/register settings to enable effective debugging.
As a successful candidate you must possess: Good understanding of IP integration and design flow challenges within the context of subsystems and SOCs.
Experience with debugging and the ability to work on a problem-solving in a team environment The ability to work independently with the design team and customers to solve remotely.
Good understanding of industry-standard IO specifications Qualifications Minimum qualifications are required to be initially considered for this position.
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications: Bachelor's degree in electrical engineering or any STEM related degree, with experience in ASIC and SoC development 6+ years of experience in RTL design using Verilog/System Verilog 2+ years of experience with VCS, Verdi, Spyglass, or equivalent tools 2+ years of experience in SOC architecture and chip-level/subsystem integration 1+ years of experience in partitioning, synthesis, floorplan, IO designs, clock tree, and timing closure for ASICs.
Preferred Qualifications: Master's degree in electrical engineering or any STEM related degree with experience in ASIC and SoC development 2+ years of experience with IP development experience is a strong plus.
2+ years of experience with ASIC synthesis flow and working with the physical design team is a plus Experience with digital flow for RTL2GDS development.
Experience with at least one or more industry-standard IO interfaces, including DDR, LPDDR, PCIE, USB, USB TypeC, Ethernet, etc.
Proficient in scripting languages like Perl/Tcl/Python and power-aware RTL and UPF flow is a plus.
Inside this Business Group IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon.
We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process.
IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving.
We are a fearless organization transforming IP development.
Other Locations US, OR, Hillsboro; US, AZ, Phoenix; US, CA, Folsom Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits We offer a total compensation package that ranks among the best in the industry.
It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.
Find more information about all of our Amazing Benefits here.
Annual Salary Range for jobs which could be performed in US, California: $144,501.
00-$217,311.
00 *Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs.
JobType Hybrid
SIPG develops a broad portfolio of IP, including FIP, analog IP, Die to Die communication.
The Customer Engineering Group (CEG) within SIPG will be a dynamic and versatile team of engineers who directly engage with both the IP design teams and external customers in all phases of development.
CEG engineers will embody customer obsession by quickly resolving customer issues and providing hands-on debugging on a wide range of technical issues spanning all design domains (logic design, timing, physical integration, emulation, documentation, and customer training).
Your job responsibilities may include but are not limited to the following: Work with cross-functional teams for IP Integration into SoC.
Engage with IP development team to ensure all IP collaterals are generated and provided.
Fully own assigned IPs and work with Internal and external customers and help them integrate Intel IPs to SoC and provide technical support.
Drive resolution of customer issues related to the IP collaterals generation, logic design verification, IP release, and integration in the SoC environment.
This may involve travel to customer sites.
Engage in the upfront identification and documentation of customer requirements, working with the IP design teams to disposition requests.
Prepare customer training materials and provide training on IP architecture, specifications, and fuse/register settings to enable effective debugging.
As a successful candidate you must possess: Good understanding of IP integration and design flow challenges within the context of subsystems and SOCs.
Experience with debugging and the ability to work on a problem-solving in a team environment The ability to work independently with the design team and customers to solve remotely.
Good understanding of industry-standard IO specifications Qualifications Minimum qualifications are required to be initially considered for this position.
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications: Bachelor's degree in electrical engineering or any STEM related degree, with experience in ASIC and SoC development 6+ years of experience in RTL design using Verilog/System Verilog 2+ years of experience with VCS, Verdi, Spyglass, or equivalent tools 2+ years of experience in SOC architecture and chip-level/subsystem integration 1+ years of experience in partitioning, synthesis, floorplan, IO designs, clock tree, and timing closure for ASICs.
Preferred Qualifications: Master's degree in electrical engineering or any STEM related degree with experience in ASIC and SoC development 2+ years of experience with IP development experience is a strong plus.
2+ years of experience with ASIC synthesis flow and working with the physical design team is a plus Experience with digital flow for RTL2GDS development.
Experience with at least one or more industry-standard IO interfaces, including DDR, LPDDR, PCIE, USB, USB TypeC, Ethernet, etc.
Proficient in scripting languages like Perl/Tcl/Python and power-aware RTL and UPF flow is a plus.
Inside this Business Group IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon.
We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process.
IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving.
We are a fearless organization transforming IP development.
Other Locations US, OR, Hillsboro; US, AZ, Phoenix; US, CA, Folsom Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits We offer a total compensation package that ranks among the best in the industry.
It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.
Find more information about all of our Amazing Benefits here.
Annual Salary Range for jobs which could be performed in US, California: $144,501.
00-$217,311.
00 *Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs.
JobType Hybrid
• Phone : NA
• Location : Phoenix, AZ
• Post ID: 9098947542
